1. Field of the invention
The present invention relates to unaligned accesses to data. More particularly, the present invention relates to unaligned accesses to data addressed in little endian and big endian format.
2. Art Background
Byte ordering determines how data is read from or written to memory and buses and ultimately how data is stored in the memory. The two byte ordering types are referred to as little endian and big endian. Little endian systems store words in which the least significant byte is at the lowest address in memory. For example, a little endian ordered word is stored at address 600. The least significant byte is stored at address 600 and the most significant byte at address 603. Big endian systems store the least significant byte at the highest byte address in memory. Therefore, if a big endian ordered word consisting of four bytes is stored at address 600, the least significant byte is stored at address 603 and the most significant byte at address 600.
Another factor to consider when addressing memory to access is whether the address is aligned or unaligned. Aligned data requests provide an address that occurs on a data type's natural boundary. Quad words and triple words are lined on 16 byte boundaries, double words on 8 byte boundaries, words on 4 byte boundaries, short words (half-words) on 2 byte boundaries, and bytes on 1 byte boundaries. Unaligned requests do not occur on these natural boundaries.
Any aligned request to a memory region is executed without modification of the access request. When the processor encounters an unaligned request, microcode breaks the unaligned request into a series of aligned requests. For example, if a read request is issued to read a little endian word from address XXXXXXX1H (unaligned), the request is executed as a byte request followed by a short request followed by a byte request. FIG. 1 illustrates how aligned and unaligned bus transfers may be carried out for memory regions that use little endian ordering.
Typically, a processor will operate in either a little endian or big endian mode and the bus attached to the processor operates in the same mode. Although some processors can operate either in the big endian mode or little endian mode, most processors typically operate in one mode and perform a translation of data received from an output to memory or other external devices prior to input to the processor. For example, processors manufactured by Intel Corporation use little endian format internally. Therefore, the processor performs operations in little endian format and likewise the internal bus which connects the processor is also little endian. Translations are performed prior to the input to the processor, for example at the bus controller, so that the addressing information is in the proper format prior to receipt by the processor.
Although translation of addresses from big endian to little endian is not immediately cumbersome, a translation of formats in conjunction with unaligned data transfers can be quite complex. Processors which support both little endian and big endian modes are able to maintain relative simplicity in translation of the data from unaligned to aligned requests. However, for processors that operate in one mode and perform translations from the second mode, the system incurs a significant cost and/or performance penalty if both modes are accepted. Many systems simply do not support unaligned accesses in the alternate data format. If a system is able to support both data format modes, the second mode is supported by causing an exception or fault and initiating specialized software to address the alignment translation for each mode. However, this significantly adds to processing overhead. Alternately, it is conceivable that specially designed hardware may be developed to handle both aligned and unaligned accesses in both modes. Such an approach however, is quite expensive due to the amount of hardware that would be required.